Mechanical Sympathy — Know the Machine (Caches, Locality, False Sharing)
Know the machine you run on
Mechanical sympathy (Martin Thompson, borrowing racing driver Jackie Stewart's phrase) is the idea that you don't have to be a hardware engineer, but you write dramatically faster code when you understand how the hardware actually behaves. The dominant fact: not all memory is equal — each level of the hierarchy is orders of magnitude slower than the one above.
The consequences that change how you write code
- Cache lines (64 bytes): memory is fetched a line at a time. Data accessed together should live together. This is why a contiguous array beats a linked list for traversal — the array is prefetched cache-line by cache-line; the list chases pointers all over RAM (cache misses).
- Sequential > random: the same reason B-trees use big pages and logs append sequentially — sequential access rides the cache/prefetcher and the disk's strengths; random access pays the full latency each time.
- False sharing (the concurrency trap): two threads writing two different variables that happen to sit on the same cache line force the line to ping-pong between cores — huge slowdown with no logical contention. Pad hot per-thread fields to separate lines. (Ties directly to the memory model.)
- Allocation & GC cost; the latency numbers (see Capacity Estimation) are the intuition you estimate with.
The mental model
When something is slow, ask "where does this data live, and am I fighting the cache / the prefetcher / the disk's sequential nature?" Often the fix is a better memory layout, not a better algorithm.
Takeaways
- The memory hierarchy is a cliff: L1 ~1ns → RAM ~100ns → disk ~10ms → cross-continent ~150ms.
- Favour contiguous/sequential layouts (arrays, batched I/O); cache lines and prefetch reward locality.
- Watch false sharing in concurrent code; layout can matter more than algorithm.
Re-authored for this guide; memory-hierarchy diagram hand-authored as SVG. Follows Martin Thompson's "mechanical sympathy" and the latency-numbers canon. See also: Capacity Estimation (latency numbers), (Concurrency) Memory Model & false sharing, How Indexes Work (pages).
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